Please use this identifier to cite or link to this item:
http://hdl.handle.net/20.500.12386/32227
Title: | FRONT END ELECTRONICS PER ASIC RENA3 | Authors: | LO GERFO, FABIO PAOLO SOTTILE, Giuseppe |
Issue Date: | 2022 | Series: | INAF Technical Reports - Rapporti Tecnici INAF | Report: | 155 | Abstract: | In questo documento verranno descritte le fasi di progettazione e test della scheda FPGA di front end, sviluppata per interfacciarci con l'ASIC RENA3. | URI: | http://hdl.handle.net/20.500.12386/32227 https://doi.org/10.20371/INAF/TechRep/155 |
Fulltext: | open |
Appears in Collections: | 4.01 Rapporti tecnici INAF |
Files in This Item:
File | Description | Size | Format | |
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5)FEE RENA3.pdf | 1.69 MB | Adobe PDF | View/Open |
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