Please use this identifier to cite or link to this item:
http://hdl.handle.net/20.500.12386/32227
DC Field | Value | Language |
---|---|---|
dc.contributor.author | LO GERFO, FABIO PAOLO | en_US |
dc.contributor.author | SOTTILE, Giuseppe | en_US |
dc.date.accessioned | 2022-06-07T15:01:39Z | - |
dc.date.available | 2022-06-07T15:01:39Z | - |
dc.date.issued | 2022 | en_US |
dc.identifier.uri | http://hdl.handle.net/20.500.12386/32227 | - |
dc.identifier.uri | https://doi.org/10.20371/INAF/TechRep/155 | - |
dc.description.abstract | In questo documento verranno descritte le fasi di progettazione e test della scheda FPGA di front end, sviluppata per interfacciarci con l'ASIC RENA3. | en_US |
dc.language.iso | ita | en_US |
dc.publisher | IASF Palermo | en_US |
dc.title | FRONT END ELECTRONICS PER ASIC RENA3 | en_US |
dc.type | Technical report | - |
dc.relation.medium | ELETTRONICO | - |
dc.relation.numberofpages | 19 | en_US |
dc.type.referee | REF_2 | - |
dc.relation.scientificsector | ING-INF/01 - ELETTRONICA | en_US |
dc.type.miur | 298 Altro | - |
dc.relation.series | INAF Technical Reports - Rapporti Tecnici INAF | - |
dc.description.oa | 1 – prodotto con file in versione Open Access (allegare il file al passo 5-Carica) | en_US |
dc.contributor.referee1 | NOGARA, PAOLO | en_US |
dc.contributor.referee2 | CORPORA, Mattia | en_US |
dc.identifier.report | 155 | * |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.openairetype | Technical report | - |
item.languageiso639-1 | it | - |
item.cerifentitytype | Publications | - |
item.grantfulltext | open | - |
item.fulltext | With Fulltext | - |
crisitem.author.dept | IASF Palermo | - |
crisitem.author.dept | IASF Palermo | - |
crisitem.author.orcid | 0000-0001-5629-1212 | - |
crisitem.author.orcid | 0000-0003-3101-3966 | - |
Appears in Collections: | 4.01 Rapporti tecnici INAF |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
5)FEE RENA3.pdf | 1.69 MB | Adobe PDF | View/Open |
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